Recently, as a CMOS semiconductor device is miniaturized, what is troubling is that a gate insulation layer composed of SiON or SiO2 becomes thin and a leak current goes through the gate insulation layer due to a tunneling phenomenon.
To solve this problem, a high-k material (high-dielectric material) such as hafnium is used for the gate insulation layer and a thickness of the gate insulation layer is set to a constant value to prevent the leak current from being generated. In addition, when the high-k material is used for a gate electrode, Fermi level pinning is generated at a boundary with a silicon gate electrode, so that as a gate electrode material, a metal such as nickel silicide is used instead of polycrystalline silicon.
For example, when the high-k material is used for the gate insulation layer, NiSi is used for a metal gate electrode of a p-channel MOSFET, and Ni2Si is used for a metal gate electrode of an n-channel MOSFET.    Patent document 1: Japanese Unexamined Patent Publication No. 2002-359295